A flash memory is a type of nonvolatile memory cell that is electrically reprogrammable. Typically, the memory cells are arranged in an array of rows and columns. These memory cells typically include floating gate transistors. These transistors can be programmed or erased by applying voltage between a control electrode and the drain, source or substrate. The voltage applied during programming (V.sub.p) or erasing (V.sub.e) is a "high" voltage, higher than the input voltage, or V.sub.cc, necessitating a charge pump to pump the voltage from V.sub.cc to V.sub.p or V.sub.e.
The charge pump increases a small input voltage (for example, V.sub.cc) into the larger voltages that are passed to the word lines and bit lines of semiconductor devices. These voltages affect the writing or erasing of data to and from the memory device. The charge pump usually includes a number of serially-connected pump stages that are driven by two non-overlapping clock signals. The serially-connected pump stages multiply the amplitude of the clock signals. The actual voltage obtained at the charge pump output terminal depends upon the number of pump stages, the clock frequency, and on the charge transfer efficiency of each pump stage.
Currently, charge pumps are constructed using several bootstrap capacitors having the same size capacitance (C) at each respective node of the charge pump. A bootstrap capacitor is simply a capacitor connected to each respective node of a charge pump.
As the input voltage V.sub.cc decreases, due to the flash memory being used in low voltage environments, such as battery operation, the number of stages necessary to generate the same high output voltages also increases. Typically, the voltage required to program or erase a flash memory array is in the range of about 10 volts.
FIG. 1 shows a conventional prior art charge pump 1. The prior art charge pump 1 consists of n stages, each stage is comprised of a diode means 2 and a capacitor 3. Typically, the diode means 2 is a field effect transistor 2 with the gate terminal connected to a source/drain terminal causing the FET to act as a diode, and the capacitor 3 is coupled to the source/drain terminal of the field effect transistor 2.
This capacitor 3 stores a charge V.sub.cc -V.sub.Th at each successive stage, thereby increasing the voltage potential by V.sub.cc -V.sub.Th at each successive stage. Thus, the current, I, across one stage n of the charge pump 1 is proportional to n(V.sub.cc -V.sub.Th), where V.sub.Th is the threshold voltage of the transistor 2 and n is the number of stages. Thus, at each stage, the voltage is pumped up proportional to n(V.sub.cc -V.sub.Th). However, in this prior art charge pump 1, reverse current flow is not prevented since adjacent transistors 2 are not switched OFF.
Thus, a drawback to prior art charge pumps is that as the number of stages increases, the power required to drive the charge pump also increases due to the increased number of capacitors in the charge pump and the reverse current flow. There is a need to reduce the size of these power supplies, by designing a more sophisticated charge pump which operates at a lower voltage than previous charge pumps, thereby reducing the amount of power needed to drive the device.
It is therefore desirable to provide a pump voltage circuit which can be used for very low voltage operation.